发明名称 STAND-BY CIRCUIT
摘要 <p>PURPOSE:To prevent the internal circuit of a microcomputer from being initialized even when the internal circuit in a stand-by state is reset by inhibiting the supply of an internal reset signal within the delay time of a delay circuit when a stand-by flag is active. CONSTITUTION:The stand-by circuit is constituted of an RS flip flop 3, a reset terminal 2, the delay circuit 4, AND gates 6, 7, 9, and a clock terminal 8. When the stand-by flag SBF is active even if the stand-by state is reset by a reset signal RES, the supply of the internal reset signal RESI is inhibited within the delay time of the circuit 4. Thereby, even when the internal circuit in the microcomputer in the stand-by state is reset, the internal circuit is not initialized.</p>
申请公布号 JPH0434612(A) 申请公布日期 1992.02.05
申请号 JP19900141924 申请日期 1990.05.31
申请人 NEC CORP 发明人 IIZUKA YUICHI;MIYATA SHINJI
分类号 G06F1/24;H03K17/22 主分类号 G06F1/24
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