| 摘要 |
<p>A two stage redundancy decoding scheme for a semiconductor memory device is disclosed. The redundant row decoder is a two stage decoder having a first redundant decoder that is programmable to hold the address of a defective row, that receives row addresses and generates redundant row decode signals and redundant row factor enable signals. The second redundant decoder is programmable to hold the location of the array containing the defective row. It receives the redundant row decode signals and produces array select signals. A third enabler stage that is connected to the redundant rows of memory cells and that is responsive to the redundant row factor enable signals and the array select signals may be added to enable the selected redundant row of memory cells of the memory array containing the defective row of memory cells. The redundant column decoder is programmable to hold the address of a defective column. It receives column addresses and generates redundant column decode signals and redundant column factor enable signals. The second redundant decoder is programmable to hold the location of the array containing the defective column. It receives the redundant column decode signals and produces array select signals. A third enabler stage that is connected to the redundant columns of memory cells and that is responsive to the redundant column factor enable signals and the array select signals may be added to enable the selected redundant column of memory cells of the memory array containing the defective column of memory cells. This decoding scheme uniquely identifies the section of memory requiring repair, thereby more efficiently using the available redundant memory cells. <IMAGE></p> |
