Bus architecture for digital communications.

摘要

In a digital communications system comprising a plurality of modules (14) plugged into slots, the backplane provides a private five-conductor data bus (12) for each module slot so that data from the modules are transmitted over separate busses. Each of the data busses is split into separately driven branches extending to the right and to the left of its corresponding module, so that the drivers are located at the ends of the branches rather than connected to an intermediate point on a bus. Pairs of slots are connected through the backplane so that, instead of having one module in each slot driving a five conductor data bus, the system can alternatively have a double-bandwidth module in every other slot driving a ten-conductor data bus made up of two five-conductor busses. Clock and synchronization signals provided by control modules are conducted to device modules over separate conductors on the backplane. The synchronization signals are encoded to represent the time within each message frame, thereby permitting synchronization within a time as short as twenty microseconds in a two millisecond frame. Reset signals for the individual modules are appended to the synchronization signals. Coordinated switch-over between two redundant control modules is effected by three voting lines controlled respectively by each control module and by all of the device modules ORed together.