| 摘要 |
PURPOSE:To attain small sized and inexpensive constitution by providing two multi-frame synchronizing circuits used for a signal in which a multi-frame pattern and a data are inserted alternately to a frame synchronizing bit location. CONSTITUTION:A 1st inverting means 10 inverts an output when an enable signal and a clock signal generated at a frame synchronizing bit location are simultaneously inputted to the means 10. A 2nd inversion means 20 inverts an output of the means 10. A 1st multi-frame synchronizing detection means 30 applies synchronization detection by using an output of the means 10 and an enable signal as a multi-frame detection signal. A 2nd multi-frame synchronizing detection means 40 applies synchronization detection by using an output of the means 20 and an enable signal as a multi-frame detection signal. An OR means 40 ORs outputs of the means 30, 40. |
