发明名称 WATCHDOG TIMER CIRCUIT
摘要 <p>PURPOSE:To set a microcomputer to a reset state even if a clock oscillation circuit is stopped by providing a private oscillation circuit. CONSTITUTION:An eight bit timer 3 where the clock input (b) of watchdog timer oscillation circuit 2 in a watchdog timer circuit 1 is set to be an input counts the input (b) for a prescribed number and an overflow signal (c) is outputted as a high level. A system reset signal (e) is outputted from a reset signal generation circuit 4 in accordance with the signal (c). Thus, the microcomputer can stable set to the reset state even if the clock oscillation circuit 6 stop by such constitution.</p>
申请公布号 JPH0433117(A) 申请公布日期 1992.02.04
申请号 JP19900139414 申请日期 1990.05.29
申请人 MITSUBISHI ELECTRIC CORP 发明人 KUROIWA MICHIAKI
分类号 G06F11/30;G06F1/06 主分类号 G06F11/30
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