| 摘要 |
<p>PURPOSE:To enable both a processor and an input/output device to have accesses to a register in a single action with no conflict by providing an arbitrating means to enable the input/output device to have an access to the register in a 1st clock state and then to enable the processor to have an access to the register in a 2nd clock state respectively. CONSTITUTION:When an access signal is outputted to a register 3 from a proces sor 1, an arbitrating means 5 stops continuously the counter operation of a 2-phase clock generator 4 until no access signal is available any more after the coincidence secured with a 2nd clock. Thus, an input/output device 2 is unable to have an access to the register 3. When an access signal is outputted to the register 3 from the device 2, the means 5 stops continuously the counter operation of the generator 4 until no access signal is available any more after the coincidence secured with a 1st clock. Thus, the processor 1 is unable to have an access to the register 3 respectively. As a result, both the processor 1 and the device 2 can have accesses to the register 3 in a single action with no conflict.</p> |
