Process for obtaining high-voltage N channel transistors particularly for EEPROM memories with CMOS technology

摘要

The process call for N- doping of a predetermined portion of a type-P semiconductor substrate preceding deposit and definition of a layer of gate polysilicon on a part of said predetermined portion and on an adjacent portion of substrate. After oxidation of the polysilicon there is performed an N+ doping in the remaining part of said predetermined portion of the substrate and of an additional substrate portion located on the opposite side of the gate.