发明名称 DATA PROCESSOR AND DATA PROCESSING SYSTEM
摘要 PURPOSE:To suppress the accumulation of jitter caused by increasing the number of data processors by selecting a clock suitable for a data to be transmitted as a third clock from a first clock generated on the inside and a second clock extracted from the input data, and defining the third clock as a reference when transmitting the data. CONSTITUTION:A clock generating means 103 generates a first clock and transmits it to a clock switching means 106, and a clock extracting means 102 extracts the second clock from the input data and transmits it to a data processing means 101 and the clock switching means 106. According to an instruction from the data processing means 101, the clock switching means 106 selects either the first clock or a second clock and outputs the selected one as the third clock. The data processing means 101 processes the input data with the second clock as a reference and prepares an output data to be transmitted with the third clock as a reference. Thus, the accumulation of jitter caused by increasing the number of data processors can be reduced.
申请公布号 JPH0433033(A) 申请公布日期 1992.02.04
申请号 JP19900135010 申请日期 1990.05.24
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MAEDA TETSUO
分类号 G06F15/16;G06F1/06;G06F1/10;G06F13/00;H03L7/06;H04L7/02;H04L12/42 主分类号 G06F15/16
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