| 摘要 |
Each programming point (11) of the programmable logic network (10) according to the invention is made with a field effect transistor (N1), the gate and drain of which are connected respectively to the input (Lx) and output (Ly) lines, and the source of which is connected both to the reference potential, via the drain-to-source path of a second field effect transistor (N2), the gate of which is connected to the output line (Ly), and to the base of a bipolar transistor Q, the emitter-to-collector path of which is disposed between the ground and output lines. A network according to the invention has an increased operating speed and can be used in a read-only memory or in PLA circuits.
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