发明名称 CORRELATION MEMORY FRAME SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To attain frame synchronization restoration in a short time when out of frame synchronism takes place by transferring a content of a 2nd correlation data storage means to a 1st correlation data storage means through a changeover means so as to detect a frame bit location. CONSTITUTION:When the result of detection of a frame pattern and an output of a 1st correlation data storage means 40 are synthesized and the result is not regarded as a frame bit, a counter means 10 shifts the clock. In this case, the synthesis of an output of a 2nd pattern detection means 30 and an output of a 2nd correlation data storage means 50 is inputted to a 1st correlation data storage detection means 40 through a changeover means 80. Then a control means 90 is stopped when the location regarded as a frame bit location is found out after the data is shifted up to the location that an output of the said detection means 20 and an output of the storage means 40 is regarded as a frame bit location so as to stop shifting the clock thereby establishing the synchronization in a short time.
申请公布号 JPH0430635(A) 申请公布日期 1992.02.03
申请号 JP19900134414 申请日期 1990.05.24
申请人 FUJITSU LTD 发明人 NAKAJIMA YOSHIYUKI
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
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