| 摘要 |
PURPOSE:To shift a digit at high speed by providing plural multiplexers constitut ing a barrel shifter in such a way that the lower multiplexer to which a bit or a bit string on a low-order side in the output of an adder-subtracter is pro vided to the more preceding stage. CONSTITUTION:The lower bit with small delay time in the outputs of the adder- subtracter 1 is inputted to the multiplexer to the more preceding stage of the barrel shifter 11. When the output of the highest bit of a shift value from the adder-subtracter 1 is decided, the input signal of the multiplexer in the final stage of the barrel shifter 11 is decided. Then, output is decided after delay time passes in the multiplexer in the final stage of the barrel shifter 11 after the output of the highest bit in the adder-subtracter 1 is decided. Consequently, the delay time when the output of the barrel shifter 11 is decided becomes the sum of the delay time required for the decision of the highest bit of the shift value from the adder-subtracter 1 and the delay time of the multiplexer in the final stage of the barrelel shifter. Thus, processing speed improves. |
