| 摘要 |
<p>A BICMOS bit line load (74) for a memory (30) with improved-speed write recovery and improved reliability. The bit line load (74) comprises first (103) and second (104) bipolar transistors coupled to first (72) and second (73) bit lines of a differential bit line pair (72, 73). The improvement in speed is accomplished through the use of the bipolar transistors (103, 104) which generally switch faster than corresponding MOS transistors. For bipolar transistors, however, mean lifetime under worst case conditions is related to reverse bias voltage by an inverse semilogarithmic relationship. The improvement in reliability occurs by limiting a reverse bias voltage to which base-emitter junctions of the bipolar transistors (103, 104) are subjected to increase the mean failure time beyond a predetermined life, for example 10 years, under worst case conditions. <IMAGE></p> |
