发明名称 EQUALIZING SYSTEM
摘要 PURPOSE:To correct the amplitude error of an output equalizing signal by supplying input signals to the serial circuit composed of plural delay means, successively delaying those signals after transmitting them forward and backward, and operating coefficients to be respectively multiplied to the input signals and delayed output signals so that the amplitude error of the output equalizing signal can be minimum. CONSTITUTION:The input signals are supplied to the serial circuit composed of plural delay means D1-Dm, and successively delayed after transmitted forward in the serial circuit, successively delayed after being transmitted backward later and further successively delayed after being transmitted forward in the serial circuit. In a tap gain control part TG, a decision signal is supplied from an error estimation part 14 so as to form coefficient signals to be respectively separately supplied to respective multiplying means M0, M1-Mm. Corresponding to the amplitude error of the output equalizing signal, the coefficients to be respectively multiplied to the input signals and the delayed output signals of the respective delay means are operated so that the amplitude error can be minimum. Thus, the amplitude error of the output equalizing signal can be corrected.
申请公布号 JPH0426216(A) 申请公布日期 1992.01.29
申请号 JP19900130752 申请日期 1990.05.21
申请人 SONY CORP 发明人 HIRAIWA HISAKI;SUZUKI MITSUHIRO;KUNIHIRO TAKUSHI
分类号 H03H21/00;H03H15/00;H03H17/00;H03H17/02;H03H17/06;H04B3/06;H04B7/005;H04L27/01;H04L27/22 主分类号 H03H21/00
代理机构 代理人
主权项
地址