| 摘要 |
A multiport cache memory for exchanging data or instructions with a plurality of arithmetic circuitries independently according to a load instruction or a store instruction provided from a CPU comprising a plurality of read only ports (PR) for respectively transmitting the data or the instructions to each arithmetic circuitry according to the load instruction, and a plurality of read/write ports (PW) for respectively transmitting the data or the instructions from/to each arithmetic circuitry according to the load or store instruction. <IMAGE>
|
