发明名称 CONTROLLING SYSTEM FOR SYNCHRONIZATION OF PLURAL PROCESSORS
摘要 <p>PURPOSE:To simplify the synchronization processing among processors without forcing the load to a control program by providing a clock switch circuit between plural processors and their clocks, and switching these clocks in the synchronization processing. CONSTITUTION:When a processing request is given to a processor 1 from another processor 1, a clock switch instruction signal is informed to a clock switch circuit 2. Then the circuit 2 works to supply the clock 3 of either one of both processors to them in common. Thus both processors 1 performs their processing synchronously with each other. That is, the circuit 2 is provided between the processors 1 and their clocks 3 and these clocks 3 are switched for execution of the synchronization processing. Thus the synchronization processing is simplified among processors 1 without forcing the load to a control program.</p>
申请公布号 JPH0424860(A) 申请公布日期 1992.01.28
申请号 JP19900129639 申请日期 1990.05.20
申请人 FUJITSU LTD 发明人 ICHIKAWA MADOKA
分类号 G06F15/16;G06F15/177 主分类号 G06F15/16
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