| 摘要 |
PURPOSE:To eliminate the need for troublesome phase adjustment between data clocks by using a clock resulting from delaying a regular clock for a prescribed time as a data read clock when a data and a data and clock are in contention. CONSTITUTION:Suppose that a shift register 4 reads a data in a rising timing of a clock CL, when a clock CL rises for a 1st pulse period, the both are in contention and the possibility of occurrence of a read error exists. Then a clock resulting from delaying a regular clock for a prescribed time is used as a data read clock. Moreover, when the clock CL rises for a 2nd pulse period, since no contention takes place, the clock CL is used as the read clock as it is. |
