| 摘要 |
PURPOSE:To evade the increase of the delay time for various control signals received from an in-circuit emulator probe by identifying all solaces based on the conditions set by the bus cycle attribute for fetch of the read and write instructions. CONSTITUTION:A microprocessor 101 reads the data on bit 1 - 0 of a firmware F/W data bus 108 when a write strobe 109 given from an F/W is active. The bit2, bit1 and bit0 of an ERW bit 107 show an instruction fetch, the read except the instruction fetch, and a 3-bit latch for write respectively. These bits are set in response to each bus cycle. Then the bit 107 is set active when an in- circuit emulator ICE mode pointing signal 110 is active. Then an ICE/USR 104 is set at 1 after a status internal signal 112 which tries to produce a set bus status and bus cycle, a read/write internal pointing signal 111, and a combination circuit 1-301 perform the comparing/deciding operations and the conditions are satisfied. |
