| 摘要 |
PURPOSE:To enable a high-speed operation of a memory cell by providing an emitter region of a load Tr in a semiconductor substrate and by forming this Tr to be of a vertical type. CONSTITUTION:P-N-P Tr is constructed of a P<+> type semiconductor layer 3 as an emitter region, an N<-> type semiconductor layer 4 as a base region and a P<-> type impurity region 5 as a collector region, while N-P-N Tr is formed of an N<+> type impurity region 7 as the emitter region, the P<-> type impurity region 5 as the base region and the n<-> type semiconductor layer 4 as the collector region. Accordingly, the lower part of the P<+> type semiconductor layer 3 to be the emitter region of the P-N-P Tr is in contact with an oxide layer 2. According to this constitution, the amount of storage charge and also the junction capacity of the emitter part can be reduced, and therefore the speed of an operation of a memory cell is made high. |
