| 摘要 |
PURPOSE:To decrease a time up to a delay RAM access by deciding it which value among plural offsets is to be used before a delay RAM access instruction. CONSTITUTION:An OFFSET RAM ADDRESS signal being an offset RAM selection signal is latched in two stages by a latch circuit 1 latching a basic address and a latch circuit 2 latching plural offsets with respect to the basic address. That is, an output of the offset RAM is decided before a delay RAM access instruction (EXR instruction) by 2 stages of latch processing in this way, and when the EXR instruction is generated, an address obtained in the latch circuit 2 is used to have only to access the delay RAM. Thus, the time from the publication of the EXR instruction till the access start to the delay RAM is decreased. |
