| 摘要 |
PURPOSE:To reduce a parasitic capacitance between bit lines near a sense amplifier and to reduce a mutual interference between adjacent bit lines by a method wherein a conductive-layer sheet which reduces a parasitic coupling capacitance is applied, via an insulating layer, to an interconnection in a bit line extension part. CONSTITUTION:A conductive-layer sheet SLD which reduces parasitic coupling capacitance CBB of an interconnection BL and the inverse of BL is applied, via an insulating layer IL2, ti a bit-line extension part CL which connects bit lines BL1 to 2 and the inverses od BL1 to 2 inside a sense amplifier SA and a memory cell array NCA. In this case, the sheet SLD surrounds the part CL from three sides; the interline coupling capacitance CBB is decreased sharply to a substantially negligible degree as compared with a case where the sheet SLD is not applied. Consequently, the limit readout sensitivity of a memory cell data can be increased. That is to say, since a mutual interference is removed by a means to install a shielding sheet also in the SA and the bit-line connecting part CL, a malfunction can be avoided even at a high-integration DRAM. Since a plane space is not required, it is possible to prevent an integration density from being lowered. |
