| 摘要 |
PURPOSE:To prevent the deterioration of the data transfer efficiency by assigning a shared memory to each optional one of plural pairs of CPUs. CONSTITUTION:The local buses connected to the microprocessors 1 - 3 are provided together with the shared memories 39 - 41 connected to the buses 48 - 50, the extension buses 45 - 47 which secure the connection between the buses 48 - 50 and the memories 39 - 41, and the extension bus interfaces 42 - 44 which secure the connection between the buses 45 - 47 and the memories 39 - 41 respectively. That is, the data communication is carried out among plural CPUs in such a constitution where a shared memory is provided to each pair of CPUs and the CPUs connected to a shared memory is turned into a single CPU. Thus it is possible to improve the efficiency of the asynchronous transfer of data carried out among optional CPUs. |
