| 摘要 |
PURPOSE:To detect a delay error in an enable or disable state by producing a test pattern which defines the expected value at the change of the output value when a test is carried out in an enable state of a clock control gate. CONSTITUTION:An enable test or a disable test is decided for a test path of a clock control circuit 4. In the enable test, the expected value is decided to define a correct state when the output of a target latch is changed. In the disable test, however, the expected value is decided to define a correct state when the output of the target latch has no change. Thus such a test pattern is produced. Then a delay test of the circuit 4 is carried out based on the test pattern. As a result, a signal data error caused between latches in an actual action can be easily detected in either an enable or disable state. |
