发明名称 PRODUCTION SYSTEM FOR CLOCK ADJUSTMENT DATA
摘要 <p>PURPOSE:To quickly produce the highly accurate data by specifying a route to adjust the clocks at a circuit part where the extracted clocks are distributed and calculating the clock delay value of the specified route. CONSTITUTION:A circuit part where the clocks are distributed is extracted out of a subject logic circuit, and a route is specified in the circuit part to adjust the clocks. Then the specified route and its clock delay value are outputted. That is, a file 26 of the data showing the logic circuit is previously stored in a storage 24. Then a route to perform the adjustment of clocks and the clock delay time of the route are obtained by a host computer 22 by reference to the contents of the file 26 and based on the terminal operation. The data on the route and the delay time obtained by the computer 22 are outputted to the storage 24 and stored in a file 28 of the output destination in a form of a list. As a result, a clock adjustment subject route is specified in a short period of time and the clock delay value of the route is obtained with high accuracy.</p>
申请公布号 JPH0423172(A) 申请公布日期 1992.01.27
申请号 JP19900128876 申请日期 1990.05.18
申请人 FUJITSU LTD 发明人 IWAKURA YOSHIYUKI
分类号 G06F1/10;G06F17/50 主分类号 G06F1/10
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