| 摘要 |
PURPOSE:To simplify the constitution of circuit and at the same time realize a high- speed operation, by using an array reverse converting circuit that converts the compressed data into an unequal length code having separated parallel bits. CONSTITUTION:The synchronous signal is detected out of the parallel 4-bit data in a memory 18 through a synchronous bit detecting circuit 19 of an unequal length code reverse converting circuit 36. The highest bit on a signal line 210 is delivered by a shifter which is controlled by a register 20 and a bit shift deciding circuit so that the highest bit becomes the 1st bit of the unequal length code that received an array reverse conversion. The output of a shifter 17 is decided by the 2nd code converter 15. Based on the result of this decision, the number of shifts is decided by a shift number deciding circuit consisting of an adder 21, a comparison/arithmetic circuit 16 and a register 22. Then the shifter 17 is controlled. Furthermore a control circuit 13 controls coders 14 and 15 based on the contents of a compressed code, and the original multi-value time series code is obtained from the coder 14 to be applied to a DPCM decoder 12. |
