发明名称 BUFFER MEMORY CONTROL SYSTEM
摘要 PURPOSE:To obtain the same effect as that of a method of increasing the number of blocks by increasing the size of address space handled with one block in a TAG2 memory. CONSTITUTION:In response to a write request from an external processor, when its address is registered in a TAG2 memory 10, a comparing circuit 11 outputs a coincidence signal and output signals from AND circuits 12-15 open an AND circuit 16, thereby sending a corresponding block address, read out from the TAG2 memory, to the processor of this system via a signal line 25 together with address low- order bits. If the write address from the external processor is not registered in the TAG2 memory 10, nothing is done. Namely, the processing of the processor of this system is not influenced.
申请公布号 JPS5730173(A) 申请公布日期 1982.02.18
申请号 JP19800103436 申请日期 1980.07.28
申请人 FUJITSU LTD 发明人 KOGA SATOSHI;UCHIDA KEIICHIROU
分类号 G06F12/08 主分类号 G06F12/08
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