发明名称 SEMICONDUCTOR MEMORY
摘要 PURPOSE:To enable the cell capacity in the same cell size larger than the capacity in the turning back bit line mode to be secured by a method wherein the bit line contact of adjacent bit lines are arranged slipping by 1/4 cell while node electrodes are set up taking polygonal projection shape rather than square shape. CONSTITUTION:Multiple cells 16-20 containing at least one each of contact 3 for node electrode and node electrode 4 as well as respectively one half of bit line contact regions 5a-5e and an active region 1 setting up one unit are arrayed respectively in A direction on the semiconductor substrate having word line 2 extended in the B direction orthogonal to an active region 1 and the long direction A of the same. Besides, within the space between the cells 16 and 17 or 18 and 19, the bit line contact regions 5a, 5b or 5c, 5d are mutually arranged in the A direction slipping by 1/4 unit. Furthermore, the node electrodes are set up taking polygonal i.e., hexagonal projection shape rather than square shape.
申请公布号 JPH0423357(A) 申请公布日期 1992.01.27
申请号 JP19900123583 申请日期 1990.05.14
申请人 SHARP CORP 发明人 YUJI TATSUYUKI;TANAKA KENICHI;MIURA ATSUSHI
分类号 H01L27/10;H01L21/8242;H01L27/108 主分类号 H01L27/10
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