| 摘要 |
PURPOSE:To reduce work memory capacity by providing work memories whose number is one larger than the number of lines required for interpolation processing. CONSTITUTION:Video digital input data of the m-th line and the (m+1)th line to the (m+4)th line are taken into work memories WM40a and WM40b to WM40e respectively through a common data bus 50 and a data bus B 51. Data outputted from the bus 51 to the bus 50 is read into a processor A 20 in the order of the m-th line in the WM40a, the (m+1)th line in the WM40b, the (m+2)th line in the WM40c, and the (m+3)th line in the WM40d. Data of the (m+4)th line is read into a processor B 21 from a WM40e, and thereafter, the same data is read in the same order as the processor A 20. Thus, the processor A 20 outputs interpolation data of the (m+1.5)th line, and the processor B 21 outputs interpolation data of the (m+2.5)th line. Hereafter, the processor A 20 outputs interpolation data of the (m+3.5)th line and the (m+5.5)th line, and the processor B 21 outputs interpolation data of the (m+4.5)th line and the (m+6.5)th line. Thus, the work memory capacity is reduced without degrading the processing performance of processors. |
