| 摘要 |
PURPOSE:To execute a comparing operation at a high speed by executing the operation in a state connecting plural arithmetic logical units based upon data size information or in a state allowing plural arithmetic logical units to be individually independent. CONSTITUTION:The arithmetic logic operation unit 9 consists of four ALUs 10 to 13 and three carrier controllers 14 to 16 to be carry propagating means connected among the ALUs 10 to 13. The controllers 14 to 16 are controlled by size information outputted from a size controller 5 and the unit 9 is divided by selectively interrupting respective elements in the unit 9 based upon the size information. When the carry of the lower side ALU passes to an upper side ALU, a lower side ALU and the upper side ALU are combined and can be regarded as one ALU. In the case of separating the lower side ALU from the upper side ALU, the carry controller transfers logical zero to the upper side ALU, so that the joined operation of respective ALUs is controlled based upon the setting of the carry controllers and operation can be executed in a data divided state. |
