| 摘要 |
PURPOSE:To reduce useless bus access and to immediately execute a processing to the abnormal bus access by providing a means to detect the abnormal bus access and a means to generate a prescribed control signal in a cache. CONSTITUTION:In a cache 2, an abnormal bus access detection circuit 10, SCe control circuit 11, SC2 control circuit 12 and SCf control circuit 13 are provided. The detection circuit 10 inputs a ready signal SCc12 and an abnormal bus access signal SCc15, detects the abnormal bus access in the case of asserting the both signals and outputs a bus access stop signal CTS. The respective control circuits 11-13 applied this stop signal CTS negate respective output signals SCe, SC2 and SCf at a high level. Thus, the useless bus access is reduced and a CPU 1 immediately executes the processing to the abnormal bus access. |
