发明名称 TRANSMISSION CIRCUIT FOR CLOCK SIGNAL
摘要 PURPOSE:To prevent an adverse effect without additional defect by clamping a signal voltage with a remote end clamping circuit and constituting a series circuit between a resistor and a capacitor of a remote end receiver so as to attain integration operation. CONSTITUTION:When a voltage higher than a signal voltage at a clamping circuit 4 due to the reflection of a clock signal is generated, a higher portion than the signal voltage is sent to a power supply side or a ground side, and the level of the clock signal is clamped to a signal voltage level. Thus, independently of the impedance of a clock signal transmission circuit 5, the level of the clock signal is fixed to a signal voltage. Moreover, the impedance of a remote end receiver 2l in the case of viewing from a quasi-remote end receiver 2ll is decreased to the resistance of a resistor 6 from an infinite value by the provision of the resistor 6. Thus, nonlinear reflection is suppressed. Thus, the adverse effect of reflection is avoided without additional defect such as susceptibility of effect of a temperature change or deteriorated high frequency response.
申请公布号 JPH0417423(A) 申请公布日期 1992.01.22
申请号 JP19900119902 申请日期 1990.05.11
申请人 FANUC LTD 发明人 SATO JUNICHI
分类号 G06F1/10;H04L7/04;H04L25/02 主分类号 G06F1/10
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