| 摘要 |
<p>A maximum likelihood detector using the Viterbi algorithm for estimating a sequence of data bits received over a communication channel. Depending on the constraint length (C), a plurality of different states is associated with the transmitted bits (e.g. 16 if C=4). The detector comprises various data sources (13, 14, 17, 23, 24, 28) relating respectively to state transition probabilities (branch metrics, previous partial path metrics) and observed values of the received bits. Means are provided for calculating the partial path metrics for each state using values from said data sources. The calculating means comprise a common adder/accumulator (1) for performing repeated additive arithmetic operations and for storing the cumulative result thereof. Multiplexing means (10-15) are also provided for selectively coupling the data sources in a predetermined order to the adder/accumulator to implement the partial path metric calculation. The architecture is compatible with VLSI techniques and enables the detector to be implemented using minimal semiconductor area. The detector may be used independently as an equaliser or a decoder but in a preferred embodiment both these functions re-use the same common hardware in series enabling both the equaliser and decoder to be implemented in a single integrated circuit (i.e. on one 'chip'). <IMAGE></p> |
