| 摘要 |
PURPOSE:To attain accurate synchronization control and bit length control for an address mark data similar to a modulated data by providing a selection section selecting either the address mark data or a data coded into a variable length constant ratio code and outputting the selected data to the system. CONSTITUTION:When a command comes from a host device, an address mark data is outputted from an address mark output circuit 4, the address mark data is selected by a selection section 3 and incorporated into a data converted into a variable length constant ratio code and the result is outputted as a write data synchronously with the system clock. The address mark data is selected in a modulation circuit 2, and in the case of the output of the data from the modulation circuit 2, the data is synchronized with the system clock independently whether the data is a data converted into the variable length constant ratio code or the address mark data. Thus, accurate synchronization control and bit length control are implemented also for the address mark data similarly to the modulated data. |
