| 摘要 |
Disclosed is a precharged-type logic circuit comprising dummy precharge lines connected to a load capacitance that is equivalent to the maximum or still larger as compared with load capacitances of respective precharge lines, wherein a precharge completion time of the dummy precharge lines is detected as a precharge completion time of the precharge lines, so that the precharge operation of the precharge lines is stopped under state of the dummy precharge line. Also disclosed is a precharged-type logic circuit comprising an AND plane having a first and a second dummy product term lines connected to a load capacitance that is equivalent to the maximum or still larger as compared with load capacitances of product term lines, wherein precharge operation of the product term lines is stopped by detecting a precharge completion time of the first dummy product term line as a precharge completion time of the product term lines, then read operation of the product term lines is started, further a discharge completion time of the second dummy product term line is detected as a discharge completion time of the product term lines, thereafter read of output lines is started. Moreover, disclosed is a precharged-type logic circuit comprising a dummy input line, wherein a discharge completion time of input lines is detected by a discharge completion time of the dummy input line, then precharge operation of product term lines is stopped under state of the dummy input line, so that read operation of the product term lines is started.
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