发明名称 CENTRAL ARITHMETIC PROCESSOR
摘要 PURPOSE:To omit the undesired accesses and to attain the high speed arithmetic processing by providing a tag flag to an internal register to show the store state of information and controlling the accesses given to a storage part and the internal register based on the information shown by the tag flag. CONSTITUTION:A CPU 1 includes a register and a tag flag provided to the register to show the presence or absence of the information. At the same time, a memory 2 is provided with a back number register. If a fact that no information is stored in the register is decided by the tag flag when a using instruction is given to the CPU 1, the addresses corresponding to a back number stored in the back number register and the position of the is register are sent to the memory 2. Then the data on the memory 2 are supplied to the CPU 1 and stored in the register. Therefore the data are obtained with an access applied to the internal register of the CPU 1. Thus the undesired accesses can be omitted and the high speed arithmetic processing is attained.
申请公布号 JPH0414147(A) 申请公布日期 1992.01.20
申请号 JP19900118254 申请日期 1990.05.07
申请人 RICOH CO LTD 发明人 YAMAURA SHINICHI;YASUI TAKASHI;YOSHIOKA KEIICHI
分类号 G06F7/00;G06F9/34;G06F9/46;G06F9/48 主分类号 G06F7/00
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