Non-volatile progammable read only memory device having memory cells each implemented by a memory transistor and a switching transistor coupled in parallel and method of memorizing a data bit.

摘要

An electrically erasable and programmable read only memory device comprises a plurality of series combinations (MB11 to MBmn) of memory cells (MC111 o MCmn3) arranged in rows and columns, bit lines (Y1 to Yn) each coupled to the front memory cells of the series combinations in one of the columns, a source line (S) coupled to the rearmost memory cells of the plurality of series combinations, and word lines (WA1 to WAm/WB1 to WBm) associated with the row of the memory cells, wherein each of the memory cells is implemented by a parallel combination of a floating gate type memory transistor (MT) and a switching transistor (ST) coupled to first and second word lines (WA1 to WAm)/WB1 to WBm), respectively, so that any memory cell is rewriteable without simultaneous erasing operation on the series combination. <IMAGE>