发明名称 DATA ORDER PROTECTING CIRCUIT
摘要 PURPOSE:To control data order at every transmission origin address and to detect an error in the data order by using the transmission origin address as an address in a memory part, storing a sequence number and comparing the stored sequence number with the sequence number of a received packet. CONSTITUTION:At the time of receiving a packet, a transmission origin address detecting part 1 detects a transmission origin address and a sequence number and stores the sequence number of the received packet by using the detected transmission origin address as the address of the memory. A data order control part 3 reads out the sequence number from the memory part 2 based upon the transmission origin address and increases the read contents. A data order monitoring part 3 compares the sequence number of the received packet with the sequence number outputted from the control part 3 to detect an error in the order of received packet. Consequently, the sequence number of each transmission origin address can be controlled, and even in the case of n:1 packet communication, the data order can be protected at every transmission origin.
申请公布号 JPH0410727(A) 申请公布日期 1992.01.14
申请号 JP19900110299 申请日期 1990.04.27
申请人 FUJITSU LTD 发明人 HIROSE TOSHIHARU
分类号 H04L12/56 主分类号 H04L12/56
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