| 摘要 |
A sampling circuit is disclosed which samples input data in synchronism with a clock pulse. The sampling circuit comprises first and second sampling units. The first sampling unit includes a first input gate for receiving input data when a clock pulse signal level is in a first state (for example, "H"), a first holding unit for receiving data via the input gate, and a first output gate for outputting hold data of the first holding unit when the clock pulse signal level is a second state (for example, "L"). The second sampling unit includes a second input gate for receiving data when the clock pulse signal level is in the second state, a second holding unit for holding the data which is received via the second input gate and a first holding unit for outputting hold data of the first holding unit when the clock pulse signal level is in the first state. According to the aforementioned circuit, an output of an unsampled one of the two sampling units is output through a corresponding output gate, and it is possible to obtain a sampling frequency which is double that of the sampling clock.
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