发明名称 SEMICONDUCTOR PACKAGE TAB TAPE
摘要 <p>PURPOSE:To prevent a semiconductor package from dropping in potential by a method wherein a first potential lead and a second potential lead are electrically connected to a first potential pattern and a second potential pattern respectively through the intermediary of through-holes selectively formed on a tape base film. CONSTITUTION:A power supply potential pattern 20 provided only to a region just under a lead 5a is formed on a second metal layer 8b located at the underside of a base film, and a ground potential pattern 10 provided to another region located at the underside of the base film 1 is formed on the second metal layer 8b. A through- hole 6 is selectively provided to the base film 1 where leads 5a and 5b are located. The lead 5a is connected to a power supply, the lead 5b is connected to a ground, and a grounding potential pattern 19 kept at a ground potential is arranged under a signal lead 4, so that the signal lead 4 is prevented from fluctuating in potential and can be easily impedance-matched to an external circuit. Not only the ground potential lead 5b is lessened in parasitic resistance through a ground potential pattern 19 but also the power supply lead 5a is decreased in resistance through the power supply potential pattern 20, in result a semiconductor package is protected against potential drop.</p>
申请公布号 JPH0410552(A) 申请公布日期 1992.01.14
申请号 JP19900111952 申请日期 1990.04.27
申请人 NEC CORP 发明人 HIRANO YOSHIYUKI
分类号 H01L21/60 主分类号 H01L21/60
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