| 摘要 |
A half tone image processing circuit in which samples of an image signal are compared with elements of a dither matrix to generate a binary image signal, and including a scale reduction circuit for canceling predetermined bits from the binary image signal to effect a reduction in size of an image produced in accordance with the binary image signal. A dither generation circuit sequentially outputs the dither elements in response to a clock signal. During scale reduction, the incrementing of the dither generation circuit is halted when samples are received that correspond to the bits to be canceled, so as to avoid picture quality degradation by maintaining continuity of the dither generation pattern.
|
