Integrated semiconductor circuit with wo voltage reception pads

摘要

The circuit comprises a first reference potential generator (5) near the first pad (2), from which is supplied with a voltage by a connecting link (4). Several second reference potential generators (6a,b) are fed with the reference potential from the first reference generator over a second link (7). Group of logic circuits (10a-d) are provided for each second reference potential generator. Each logic circuit has a switching circuit for processing an input signal, using the second reference potential, supplied via a third link (8a,b), forming a logic threshold value. Each second reference potential generator is formed near the respective group of logic circuits for reducing the resistance of the third link.