| 摘要 |
The circuit detects the phase of clock signal included in received data exactly to improve Jitter characteristics and has a function to hold the phase of data transition point when the logical value of input data is not changed. The circuit includes a bi-directional one shot (14) for detecting the zero point passing of input data, a uni-directional one shot (15) triggered by zero point passing signal to generate frequency dividing start signal, a frequency divider (17) initialized by the start signal of the unidirectional one shot (15) to count the clock signal so that input data clock signal is recovered, an adder (18) for generating on-off control signal to eliminate the impulse noise included in the output signal of the frequency divider (17), and a switch (19) for applying output signal of the divider (17) to phase locked loop (PLL).
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