| 摘要 |
<p>In a 2-D graphics rendering system having a plurality of processors (PROC 0 to PROC 3) which receive instructions from a common instruction register (IR) and render polygons in a framestore (FS), in order to permit asynchronous performance of the instructions and yet ensure that overlapping polygons are properly rendered, each instruction includes an ordering code, and before writing a pixel to the framestore (FS) each processor checks that the ordering code of the polygon it is rendering is more significant than an ordering code for that pixel stored in an ordering buffer in which case the pixel is written to the framestore (FS) and the order buffer (OB) is updated, but if not the pixel is not written.</p> |
