| 摘要 |
PURPOSE:To realize a phase synchronization circuit whose memory capacity is less when a phase fluctuation is recognized in advance by dividing a frame of a digital signal into plural blocks larger than a clock phase fluctuation width recognized in advance and applying write/read to/from a frame synchronization memory for each block. CONSTITUTION:A capacity of a memory 1 is expressed in M/N (=integral number) bits, where the size of a frame is M bits and N is number of divisions. An input PCM signal from a transmission line is written in the memory 1 in a timing when a phase synchronization pulse detected from the input PCM signal by a frame synchronizing circuit 2 is written in the memory 1 and the signal in the memory 1 is read with a delay in several bits from the write timing. Then write/read address counters 3,4 are both run freely in the timing when no phase synchronization pulse is reached. Thus, number of divisions has only to be set below M/(2Xd) in the system in which the relative phase fluctuation is d-bit or below and when the relative phase fluctuation (d) is small, number of divisions N is increased to reduce the required capacity of the memory 1. |
