| 摘要 |
<p>A multiport memory includes first P-stage registers (R1, R2, R3) connected to either the row or column lines of a semiconductor memory (1), P second registers (SR1, SR2, SR3) respectively connected to outputs of the first P-stage registers and permitting a serial shift, P ports from the second registers and control means 4 for causing an address corresponding to the ports to be given to the memory selectively, for causing a parallel load into the first registers or the second registers and for causing a shift operation within the first registers. <IMAGE></p> |
