| 摘要 |
<p>An integrated circuit design and method for its fabrication are disclosed. A bilevel-dielectric (e.g., 33, 35) is formed to cover the active regions of a transistor and raised topographic features such as a gate runner (e.g., 31 ). The upper level (e.g., 35) of the dielectric is planarized to provide for easier subsequent multilevel-conductor processing. Windows (e.g., 43, 41) are opened in the bilayer dielectric by etching through the upper level (e.g., 35) of the dielectric, stopping on the lower level (e.g., 33) of the dielectric. Then the etch procedure is continued to etch through the lower level (e.g., 33) of the dielectric. <IMAGE></p> |
