| 摘要 |
<p>Tap arithmetic units (50) and first delay circuits are arranged alternately. Each of the tap arithmetic units (50) comprises a full-adder array (50a) for multiplying an input signal which has been sampled at regular intervals and coefficients, a second pipeline delay circuit (50b) for delaying outputs of the full-adder array (50a) by a predetermined time and an adder circuit (50c) for adding outputs of the second delay circuit (50b). The first and second delay circuits (50b) are timed to the preceding tap arithmetic unit for arithmetic operations. The use of the second delay circuit (50b) for the timing of arithmetic operations permits the arrangement of the first delay circuit to be simplified. <IMAGE></p> |
