| 摘要 |
<p>A semiconductor memory device having: a first power source (P1) having a non-ground potential Vcc1 terminal and a ground potential Vss1 terminal; the internal circuit (10) being supplied with power from the power source (P1) dedicated to the internal circuit, the internal circuit selecting a memory cell (MC) of a memory cell array (4) in accordance with an inputted address (A1, A2) and having a first output terminal (1) and a second output terminal (2), and the first output terminal outputting one of the pair of potentials Vcc1 and Vss1 and the second output terminal outputting the other of the pair, in accordance with the data in the selected memory cell; a second power source (P2) output circuit (20) and having a non-ground potential Vcc2 terminal and a ground potential Vss2 terminal; and the output circuit being supplied with power from the power source dedicated to the output circuit, the output circuit having first and second transistors (T1, T0) serially connected between the Vcc2 terminal and Vss2 terminal, the control terminals of the first and second transistors being connected to the first and second output terminals (1, 2), and having a third transistor (T2) being connected between an interconnection between the first and second transistors connected to a data output terminal (Dout) from which data is externally outputted, and the first output terminal, and the control terminal of the third transistor being connected to the second output terminal (2). <IMAGE></p> |
