发明名称 PHASE LOCK LOOP CIRCUIT
摘要 PURPOSE:To shorten a leading-in time, by measuring a period of an input signal when an operation is started, converting this measuring signal to DC, and applying it to a voltage control oscillator VCO. CONSTITUTION:When an operation is started, a counter 7 counts an interval of an input signal by a clock from a clock terminal 10. An output of the counter 7 is provided to a holding circuit 9 is converted to DC voltage and is held. This DC voltage is applied to a VCO3, and also the VCO3 is reset by a controlling circuit for presetting 6. Voltage which is applied to the VCO3 by the next input signal is changed over to an output of a low-pass filter 2 by a switching circuit 5. That s to say, since the output of the VCO3 almost coincides with the input signal in advance, it attains to a lock state in a short time.
申请公布号 JPS5741042(A) 申请公布日期 1982.03.06
申请号 JP19800117401 申请日期 1980.08.26
申请人 NIPPON DENKI KK 发明人 MASUMOTO YOSHINARI
分类号 H03L7/113;H03L7/10 主分类号 H03L7/113
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