COMPLEMENTARY LOGICAL GATE DEVICE

摘要

Provided is a complementary logical gate device represented by a silicon CMOS logical circuit among semiconductor integrated logical circuits which can effectively solve the problem of the speed performance limit of an ultra-large scale integration and an ultra-low power consumption type logical circuit. The complementary logical gate includes an electron running layer formed by grapheme (33) without using an n-channel FET or a p-channel FET, has the ambipolar characteristic, and uses only two FET having different threshold values, i.e., a first FET (1) and a second FET (2).  The first FET (1) has a gate electrode (11) short-circuited to a gate electrode (21) of the second FET (2) so as to constitute an input terminal.  The first FET (1) has a source electrode (12) set to a low potential.  The first FET (1) has a drain electrode (13) connected to a source electrode (22) of the second FET (2) so as to constitute an output terminal.  The second FET (2) has a drain electrode (23) set to a high potential.