发明名称 PLL FREQUENCY SYNTHESIZER
摘要 PURPOSE:To quicken the switching of the frequency by providing a 2nd phase frequency comparator and a 2nd variable frequency divider in addition to a 1st phase frequency comparator being the component of a phase locked loop, and switching the time constant of a loop filter depending on the output of the 2nd phase frequency comparator. CONSTITUTION:The output of a voltage controlled oscillator 4 is inputted to a 1st variable frequency divider 5, in which the signal is frequency-divided according to a frequency division number represented by a frequency division number 8, the output of a reference frequency oscillator 2 is frequency-divided at a fixed frequency divider 3 and the frequency division outputs are compared by a 1st phase frequency comparator 1. On the other hand, the output of the voltage controlled oscillator 4 is inputted simultaneously to a 2nd variable frequency divider 10, in which the signal is frequency- divided according to a frequency division number represented by a frequency division data input 11 and the result is compared with the output from the reference frequency oscillator 2 being frequency-divided at the fixed frequency divider 3 at the 2nd phase frequency comparator 9. When the deviation of both the outputs is smaller than a prescribed value, the time constant of a loop filter 7 is switched. Thus, the switching timing of the time constant of the loop filter is quickened to reduce the lock time of the phase locked loop.
申请公布号 JPH042218(A) 申请公布日期 1992.01.07
申请号 JP19900103414 申请日期 1990.04.19
申请人 NEC CORP 发明人 NORIMATSU HIDEHIKO
分类号 H03L7/087;H03L7/089;H03L7/095;H03L7/107;H03L7/18;H03L7/183 主分类号 H03L7/087
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